Journal of Signal Processing and Wireless Networks

Abstract

Multilevel inverter is used in applications that need high voltage and high current. The topologies of multilevel inverter have several advantages such as lower total harmonic distortion (THD), lower electromagnetic interference (EMI) generation, and high output voltage. The main feature of multilevel inverter is the ability to reduce the voltage stress on each power device due to the utilization of multilevel on the DC bus. The advent of multilevel inverter topologies has caused variety of pulse width modulation strategies. In this paper, various multi carrier pulse width modulation techniques are proposed, which can minimize the total harmonic distortion and enhances the output voltages from seven levels inverter. Three methodologies adopting the phase disposition (PD), Phase Opposition Disposition (POD) and Alternative Phase Opposition Disposition Pulse width modulation (APOD) concepts are proposed in this paper. Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast prototyping, simple hardware and software design. The simulation and experimental results are presented.

Research Highlights

Three methodologies adopting the phase disposition (PD), Phase Opposition Disposition (POD) and Alternative Phase Opposition Disposition Pulse width modulation (APOD) concepts are proposed in this paper.

Field programmable gate array (FPGA) has been chosen to implement the pulse width modulation due its fast prototyping, simple hardware and software design.

The simulation and experimental results are presented.

Analysis of THD for Cascaded H Bridge Inverter Topology with Reduced Number of Switches using Multicarrier Pulse Width Modulation Techniques

Abstract

Multipath routing protocols are progressively increasing the network lifetime by share out the traffic between numerous paths. To extend the load between different nodes, node disjoint multiple paths are implemented for data communication. In such networks attaining Quality of Service (QoS) routing is a difficult task due to the network breakage by node mobility or high power consumption of mobile nodes. This paper presents a new adaptation of Power Aware QoS Management in Node- Disjoint Multipath Routing Protocol (PAQM-NDMRP) incorporated with cluster head selection in clusters to allow the sharp selection of node- disjoint routes, and these node-disjoint routes are selected in various cluster head at clusters from the environment circumstance of the network to satisfy the QoS requirements. The performance of our protocol is contrasted with PAQM-NDMRP. From simulation results attained from NS2 simulator by implementing the proposed method, show improved result in terms of power consumption, end- to-end delay, energy consumption, node mobility and throughput as compared to PAQM-NDMRP.

Research Highlights

The performance of our protocol is contrasted with PAQM-NDMRP. From simulation results attained from NS2 simulator by implementing the proposed method, show improved result in terms of power consumption, end- to-end delay, energy consumption, node mobility and throughput as compared to PAQM-NDMRP.

Power Aware QoS Enabled Node-Disjoint Multipath Routing Protocol for MANET

Abstract

Wearable technology plays a prominent role in today’s healthcare transformation. Recent advances in telecommunications, microelectronics, sensor manufacturing and data analysis techniques have opened up new possibilities for using wearable technology in digital health ecosystem. Sensors and wearables allow continuous physiological monitoring with reduced manual intervention and at low cost. By combining physiological sensors with activity monitors and consumer-end electronic devices, this application of digital health can be used for early detection of symptoms and adverse changes in a patient’s health status—expediting timely medical interventions. Conventional methods require a hospital environment, special equipment and direct skin contact with 12 electrodes. This project aims to build a wearable mobile ECG monitoring system that overcomes these limitations by reducing the number of electrodes, cutting the heavily wired system and thereby reducing the total cost.

Research Highlights

Conventional methods require a hospital environment, special equipment and direct skin contact with 12 electrodes.

This project aims to build a wearable mobile ECG monitoring system that overcomes these limitations by reducing the number of electrodes, cutting the heavily wired system and thereby reducing the total cost.

Wearable Mobile ECG Monitoring System

Abstract

Bus Location Tracking System using Android is a mobile application for bus location identification by using mobile GPS. If may be any traffic or late in bus arrived time, we know that by other persons only. By using this application we can easily identify the current location of the bus without any ones help. By using Bus Location Tracking we can easily get the current location of the bus in message format. First we register the bus number in the Register field by providing the Bus number and admin number. Then the bus will be registered to the application. The bus will be tracked by the event of pressing track bus button. It will work based on the GPS signal. By the help of Android Location Manager we get the current Latitude and Longitude of the bus. Then it will send to the admin number. By using these Proximate values we provide the location of current place of the bus. Then the notification will be sent to the student‟s mobile. To avoid the cost of SMS notification are sent. Current place will be displayed by the help of track option.

Research Highlights

Then it will send to the admin number. By using these Proximate values we provide the location of current place of the bus.

Then the notification will be sent to the student‟s mobile. To avoid the cost of SMS notification are sent. Current place will be displayed by the help of track option.

Tracking of the Bus Location Using Android Applications

Abstract

Emerging nonvolatile memories (NVMs), such as MRAM, PRAM, and RRAM, have been widely investigated to replace SRAM as the configuration bits in field-programmable gate arrays (FPGAs) for high security and instant power ON. However, the variations inherent in NVMs and advanced logic process bring reliability issue to FPGAs. In this work, we propose a novel peripheral circuit for DRAM. A new scheme that supports dynamic RAM is introduced. The salient features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits, and low leakage current, most of these have get give a better advantage. The DRAM (dynamic random access memory) has been implemented by using a self controllable voltage level technique. It has been found that this technique reduces the leakage current and produces the high performance as compared with existing techniques. The reliable to the read and write operation.

Research Highlights

The DRAM (dynamic random access memory) has been implemented by using a self controllable voltage level technique.

It has been found that this technique reduces the leakage current and produces the high performance as compared with existing techniques.

The reliable to the read and write operation.

Low Power Variation Using Dynamic Random Access Memory Technique