Past Issue


Vol. 3 No. 1 2018

MVFB: An Efficient Modified Variable Filter Bank Design with Warped Filters Original Research Article

Pages 01-04
N. Subbulakshmi, Manimegalai

Abstract

This paper focuses on the implementation of efficient and adaptive warped filters with better accuracy. The filter provides the decimated version of the original frequency response through the co-efficient decimation technique. First, a single multiplier structure is designed and then, it is configured into the modified variable filter bank structure. The filter design proposed in this paper is more efficient in terms of area and power with less hardware complexity and can be used in audio signal processing applications. The proposed warped filter provides frequency responses of low-pass, high-pass, band-pass and band-stop filters. The input-output characteristics of the designed filters are also analyzed in this paper. The designed warped filter is controlled by changing the coefficient of the warped filter which decreases the complexity of the filter bank. This filter bank can be used in various applications such as noise reduction, linear prediction and sub-band coding. The proposed MVFB filter design is implemented in Xilinx Vertex - 5 FPGA kit. The experimental results obtained indicate that the proposed MVFB filter design achieves a substantial computational savings.

Research Highlights

We have proposed an efficient filter bank structure with warped filter for audio and speech processing applications.

The proposed filter is implemented in Vertex - 5 FPGA

Optimization of the filters is possible using advanced schemes which could further reduce the complexity of the filters.

MVFB: An Efficient Modified Variable Filter Bank Design with Warped Filters

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Certain Investigations and Comparative Analysis of Low Voltage High Speed SRAM Bit Cells for Low Power Applications Original Research Article

Pages 05-08
N. Deepak, R. Barathraj, P. Kavin Raj, E. Hari Krishnana

Abstract

A design of a 6T, 7T &Schmitt trigger SRAM bit cell that targeted at low voltage functionality while maintaining high soft-error robustness in designed with low power sensor amplifier and address decoder. A radiation tolerant bit cell, specifically designed for low-voltage operation, is proposed. The 13T dual-driven separated-feedback bit cell employs several novel techniques to achieve robust SEU suppression. The proposed radiation hardened bit cell is a pioneer solution for embedded memories in low-power space applications. In this paper, Tanner EDA version 13.0 in 22nm technology is used. Implementation of SRAM arrays based on the proposed bit cell reduces area and power consumption by 30% compared with the common TMR approach.

Research Highlights

We have proposed a 6T, 7T and Schmitt trigger SRAM bit cell, designed for robust, low-voltage, ULP operation in high radiation environments, such as those encountered by space applications.

Layout techniques were implemented in order to decrease SEU probability, while maintaining a bit cell area much smaller than alternative solutions.

Certain Investigations and Comparative Analysis of Low Voltage High Speed SRAM Bit Cells for Low Power Applications

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Low Power Reversible Modified SQRT CSLA Design Using D-latch & BK adder Original Research Article

Pages 09-16
Athira V. S, R. Arun Sekar, Monisha Thangavel, Karthikeyani Velusamy

Abstract

The basic building blocks of any processor is adders and in VLSI design the adders are used as fundamental requirements to achieve high performance processors and multi-core devices. To acquire fast arithmetic functions in many processors, fastest adder carry select adder is used. For the construction of low power and low energy loss in arithmetic circuit, reversible logic is introduced. Reversible logic egressed as low power technology. The power dissipation will occur only when bits are loss during process. In this paper carry select adder is designed with reversible logic to abridge power loss. Conventional CSLA designs developed like Modified SQRT CSLA (MCSLA), Binary to excess one converter based CSLA and D-latch and Brent Kung based CSLA. Various design of reversible logic gates used for reversible operations and implemented in carry select adder blocks, which shows better performance in terms of power and area. In this paper different models of 16 bit carry select adder with reversible logic have been analyzed based on parameters like power, area of utilization and speed. The design is written in Verilog Hardware Description Language (HDL) and synthesized using Xilinx ISE 14.5.



Research Highlights

We have proposed the design of Carry Select Adder with reversible logic to abridge power loss.

Various design of reversible logic gates used for reversible operations and implemented in carry select adder blocks, which shows better performance in terms of power and area.

Also we have analyzed different models of 16 bit carry select adder with reversible logic based on parameters like power, area of utilization and speed.

Low Power Reversible Modified SQRT CSLA Design Using D-latch & BK adder

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Human Age Recognition from Facial Images in Image Processing using MATLAB Original Research Article

Pages 17-20
K.R.Prabha, B.Chitra, M.Gowsalya, T.Janani

Abstract

There has been a growing interest in automatic age estimation from facial images due to variety of application such as security control ,law enforcement. Automatic age recognition still remains a problem. approach as stand-alone systems, include an initial search over a large face database to index candidates who then are subject to a more accurate .These approaches are very practical, easy to analyze and therefore they allow fast algorithms and show sufficiently high accuracy. In this paper ,MATLAB is used. Implementation of Local Binary Pattern and Gray Level Co-occurrence Matrix proves to support any kind of facial image that belong to any nativity.










Research Highlights

We have proposed an efficient method of estimating the human age using the facial images through Local Binary Pattern and Gray Level Co-occurrence Matrix.

This method has an advantage of estimating the age of people despite of their nativity and the performance is better when compared with other methods.

Further accuracy level can be increased by using more number of images in the database.

Human Age Recognition from Facial Images in Image Processing using MATLAB

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A New Redundant Binary Partial Product Multiplier Original Research Article

Pages 21-26
Shankari C, Jagdesh M, Kirithika Sigamani, Kirubhasudha Nagarajan

Abstract

Multiplication is one of the basic operation in digital signal processing, multimedia& microprocessor. Redundant binary multipliers are widely used for high speed multiplication. The conventional multiplier requires an additional redundant binary (RB) product because a error correcting word is generated by both radix-4 modified booth and encoding & RB encoding. Here a new RB radix-4 booth encoding partial product generator is used. RB multiplier is used in multiplier with operand without increasing the delay of partial product. It removes extra error correcting word (ECW) and saves one stage of redundant binary partial product (RBPP).The stage count is decreased. The power delay is reduced using the modified RB multiplier when comparing the conventional multiplier. Pipelining is used for removing additional stages in the process. Simulation results have been Multiplication operation product is obtained by adding partial product. It improves the area and power consumption. It results in the improvements of complexity and critical path delay for a RB multiplier.






Research Highlights

The DRAM (dynamic random access memory) has been implemented by using a self controllable voltage level technique.

We have proposed a new modified RBPP generator to eliminate and RBPP accumulation stage is saved due to the elimination of ECW.

The proposed designs achieve significant reductions in area and power consumption when the word length is at least 64 bits.

A New Redundant Binary Partial Product Multiplier

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Design Analysis of CMOS Circuit Using Sub Clock Power Gating Technique Original Research Article

Pages 27-30
Saravanan. M., Santhosh Kumar. A, Komala. N, Koshicka. M, Mallika. S and Mythili Kanmani. K

Abstract

Reducing the power consumed by the device is the emerging trend now-a-days. The aim is to reduce the leakage current of the circuit by using the Sub Clocking technology. It is the process of switching the circuit by means of partially ON to reduce the power consumption. There are two modes of operation are implemented. Half Mode Operation (HMO), Full Mode Operation (FMO). These modes of operation are implemented in the two designing methods One is Design-I,In that pMOS and nMOS are connected at header side of the standard CMOS circuit. In Design-II pMOS and nMOS are connected at the footer side of the standard CMOS circuit. pMOS and nMOS transistor at the header and footer side are refer to be as a Sub Clock control unit. Any one of the transistor is ON for a half mode operation and both the transistor are turn ON for full mode of operation. This will do by using the control signal to the sub clock unit which is placed in either header side or footer side of the CMOS gate. By this process the power consumed by the gate is reduced and also reduce the power leakage during the ideal mode of the gate.






Research Highlights

The proposed Sub Clocking technique reduces a power, consumed by the device during the Active mode and also in Ideal mode.

Design-I approach use to reduce the power consumption by means of voltage dividing process and design-II approach used to reduce the leakage current during the high speed switching.

Compare to the DML logic the sub clocking method of design reduce the power consumed by a gates up to 10%.

Design Analysis of CMOS Circuit Using Sub Clock Power Gating Technique

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A Survival Study of Security Attacks Security Mechanisms and Security Challenges in Network Security Original Research Article

Pages 31-36
Jayasmruthi A, Parthasarathy P

Abstract

Computer has become an incorporated part of our current life style. Nearly all activities are dependent on the Computers, like Communication, Ticket Reservations, Researches, Printing, and Education etc. When we circulate with each other by using Computers through E Mails, a number of Computers are used for this function and the anthology of these computers forms a network, which is called a Computer Network. As more peoples are going to be linked through the universal network (INTERNET), the crisis of security arises. Network Security is the succession of taking physical and software contraceptive occasion to preserve the lurking networking substructure from unauthorized access, misuse, malfunction, modification, demolition, or imprudent deterration, thus build up a cloistered gibbet for computers, tenants and programmers to execute their essential operations. With the concurrence of the internet, security has become a premier contention in the approaching course of action.. Networks are laid bare to attacks because of security ruptures. To avoid these objectionable acts, cryptography is used to guarantee security of the hidden and locked message. In this research work ample assortment of network attacks and diverse securities to exploit those attacks are dissipated.






Research Highlights

We have presented the detailed survey on some of the basic concepts in cryptography, and some of the essential parameters that are used in cryptography.

As the significance and magnitude of privacy of data is continuously increasing, the value of network security and cryptography is increasing laterally.

This survey will hopefully prompt future researchers to come up with adequate and more vigorous security mechanisms and make their network free from danger.

A Survival Study of Security Attacks Security Mechanisms and Security Challenges in Network Security

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Implementation of High Speed 32 Bit Kogge Stone Adder Original Research ArticleOriginal Research Article

Pages 37-40
Anitha M, Sathish Kumar

Abstract

An important component of digital computers is adders. Adders are used in many different parts of the digital computer. They are not only used in the Arithmetic Logic Unit (ALU) but also in address calculation. Adders are also used in multipliers and other functional units. One of the Most Prominent adders In VLSI Industry is Parallel Prefix adders. The Parallel Prefix Adder (PPA) is one of the fastest types of adder that had been created and developed. One of the common types of parallel prefix adder is Kogge Stone adder. In existing system by using the Xilinx 14.1 software, the designs for Kogge Stone adders was developed for 8-bit.This paper focuses on the implementation and simulation of 16-bit and 32 bit Kogge adder based on Verilog code and compared for their performance in Xilinx. Hence, this paper is significant in showing which of the adder being tested perform better in terms of computational delay based on different sizes of bits.






Research Highlights

We have implemented High Speed 32 bit Kogge Stone Adder by utilizing a generate and propagate signals in the first stage, then there are used to compute the intermediate carries in parallel.

The advanced Kogge-Stone parallel prefix adder provides O(log2N) latency, producing a critical path delay twelve times less than the standard Ripple Carry topology.

In future it would be interesting to design 64 bit and 128 bit kogge stone adders combined with other different types of adders.

Implementation of High Speed 32 Bit Kogge Stone Adder Original Research Article

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A Position Sensorless Control of Brushless DC Motor for Variable Speed ApplicationOriginal Research Article

Pages 41-44
S. Gokul, M. Karthik, R. Nithyadevi, V. Poorani

Abstract

To manage Permanent magnet brushless DC motors, position and speed sensors are vital because the current should be restricted depending on the rotor position. Moreover, these sensors are adverse from standpoints of size, cost, maintenance, and reliability. There are dissimilar ways of approaching this problem, depending on the flux distribution. The paper presents the speed and position sensor less control of PM brushless DC motors with a sinusoidal flux distribution. The starting procedure is also a very difficult problem under sensor less drives, because the sensor less drive algorithm uses voltage and current for estimation of rotor position, but no information is available before starting. At first two phases of brushless DC motor is energized. According to the rotor position of that energized phases, the commutation sequence is performed. It is purely an open loop control and the speed of the brushless DC motor can be varied by changing the frequency of the pulse width. The pulse width modulation signals for six MOSFET’s are generated using Atmega 8L microcontroller.






Research Highlights

We have proposed the speed and position sensor less control of PM brushless DC motors with a sinusoidal flux distribution.

According to the rotor position of that energized phases, the commutation sequence is performed.

The pulse width modulation signals for six MOSFET’s are generated using Atmega 8L microcontroller.

A Position Sensorless Control of Brushless DC Motor for Variable Speed Application

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